Metal etching method for an interconnect structure and metal interconnect structure obtained by such method

ABSTRACT

A metal interconnects structure, comprises a substrate ( 11 ), a dielectric layer ( 12 ) lying above the substrate, a stop layer ( 13 ) for metal etching lying above the dielectric layer, a metal layer ( 15 ′) lying above the stop layer, said metal layer being patterned according to a desired pattern.

The present invention relates to a subtractive method for manufacturinga metal interconnect structure for use in a semiconductor device or thelike, a metal interconnect structure obtained by such method, and asemiconductor device, an integrated circuit chip and an electronicapparatus comprising such a structure.

It finds applications, in particular, in the field of manufacturing ofsemiconductor devices.

A method for manufacturing a metal interconnects structure using asubstractive method typically comprises a step of plasma etching of ametal layer through a patterned resist layer (resist mask). Typically,the main etch has a large microloading, i.e., more metal remains indense areas than in open areas. Therefore, the overetch has to be longto ensure the removal of any residual metal. At the same time, theoveretch is supposed to remove the conductive glue and/or barrier layer,typically titanium nitride (TiN) and/or titanium (Ti), at the bottom ofthe metal stack. This is established by increasing the physicalcomponent of the overetch compared to the main etch. The increasedphysical nature of the overetch reduces the selectivity to theunderlying dielectric layer. The underlying dielectric layer is made ofan insulating oxide material, typically silicon oxide (SiO2).

Because of the aforementioned microloading effect the consumption of theunderlying dielectric layer is larger in open areas than in dense areas.As a result, the planarity of the wafer decreases. At the same time,etching the oxide layer increases the oxygen content of the plasmathereby greatly reducing the selectivity to resist (selectivity decreaseis about a factor 4). This can lead, locally, to the complete erosion ofthe resist mask, and hence to the etching of the top corners of themetal patterns. These drawbacks are emphasized where the overetch timeis increased or its physical component enhanced.

An object of the present invention is to overcome the above-mentionedproblems of the related art.

This is achieved, according to the present invention, by depositing astop layer above the dielectric layer, which exhibits a lower etch ratecompared to the dielectric layer. This stop layer is deposited beforedeposition of the metal layer to be etched. It is then used as stoplayer for metal etching. For Al or W etching, this stop layer ispreferably made of silicon carbide (SiC). However, the invention is notintended to be limited to this example.

The use of SiC as an etch stop layer is known in the prior art, e.g.from the international patent application WO 99/33102. This known use,however, is restricted to a specific application, that is etching ofdielectric films to define vertical and horizontal interconnectsaccording to the well-known dual 15 damascene technique. This techniqueis used to form metal interconnects by etching a dielectric (typicallysilicon oxide) layer to define both vertical and horizontalinterconnects, then by inlaying metal into the defined patterns, andfinally by removing any excess metal from the top of the structure in aplanarization process. In this application, SiC may be selected as anetch stop layer for dielectric etching, because of its low dielectricconstant (low-k). Such low-k property allows to reduce the capacitivecoupling between interconnect lines, which may lead to cross talk and/orresistance-capacitance (RC) delay and hence degrade the overallperformance of the device.

The present invention is directed to a totally different application,i.e. traditional metal deposition/etching process for subtractiveforming of metal interconnects.

A first aspect of the invention thus relates to a subtractive method ofmanufacturing a metal interconnect structure on a substrate, comprisingthe steps of:

-   -   depositing a dielectric layer above the substrate;    -   depositing a stop layer above the dielectric layer, which        exhibits a lower etch rate compared to the dielectric layer;    -   depositing a metal layer above the stop layer;    -   depositing a first resist layer above the metal layer;    -   patterning the first resist layer according to a first desired        pattern; and,    -   etching the metal layer through the patterned first resist        layer, while stopping on the stop layer.

Where the metal layer is typically an Al, W, copper (Cu), Ti, TiN,tantalum (Ta), or tantalum nitrite (TaN) layer and combinations thereof,the stop layer material is preferably a silicon and carbon-containingmaterial, e.g. selected from the group comprising silicon carbide (SiC),nitrogen-containing SiC (SiCN), and boron-containing (SiBC),boron-containing SiCN (SiBCN).

The erosion of the underlying dielectric layer during metal etching islimited thanks to the lower etch rate of the stop layer. As a result,the device exhibits improved planarity after etch. Furthermore, theselectivity to resist is preserved because the underlying dielectriclayer is not exposed to the plasma whereby no erosion of the top cornersof the metal patterns is observed.

Another aspect of the invention relates to a metal interconnectstructure obtained by a method according to the first aspect. Thestructure comprises:

-   -   a substrate;    -   a dielectric layer lying above the substrate;    -   a stop layer for metal etching lying above the dielectric layer        which exhibits a lower etch rate compared to dielectric layer;    -   a metal layer lying above the stop layer;

said metal layer being patterned according to a first desired pattern.

Where the structure comprises vertical interconnects (contacts and/orvias), said dielectric layer and said stop layer may be both patternedaccording to a second desired pattern.

Another aspect of the invention relates to a semiconductor devicecomprising an interconnect structure according to the second aspect.

Another aspect of the invention relates to an integrated circuit chipcomprising an interconnect structure according to the second aspect.

Another aspect of the invention relates to an electronic apparatuscomprising an interconnect structure according to the second aspect, asemiconductor device according to the third aspect, or an integratedcircuit chip according to the fourth aspect. Such electronic apparatusmay be a cellular 4 phone, a general purpose computer, a personaldigital assistant (IDA), a DVD (Digital Versatile disc) player, or thelike.

Other features, advantages and/or objects of the invention will becomemore apparent from the following detailed description of embodimentsthereof. This description is given with reference to the appendeddrawings wherein:

FIGS. 1A through 1H are cross-sectional diagrams illustrating a portionof a semiconductor device at respective steps of an exemplary embodimentof the manufacturing method according to the invention;

FIG. 2 is a flow chart illustrating steps of an exemplary embodiment ofthe method according to the invention.

In the drawings, like reference numbers designate like parts in variousFigures.

It is primarily to be observed that the invention relates to atraditional subtractive method for manufacturing a metal interconnectstructure for use in a semiconductor device. Subtractive methodscomprise a step of etching trenches (for wiring) in a metal layercorresponding to a given metallization level. Such method is not to beconfused with the alternative well-known damascene or dual-damascenetechniques, where interlevel or intralevel dielectric layers are etchedinstead of metal layers.

The device is typically an integrated circuit chip. By integratedcircuit, it must be understood an electrical circuit formed entirely bysemiconductor technology on a single chip. Of course, it is noted thatthe invention is not in any way intended to be limited to this example,but encompasses applications wherein, for example, the device isincorporated in a hybrid circuit, in a multichip module (CM), or mounteddirectly on a printed circuit board (Chip-On-Board, or COB).

The steps of the method will now be explained with reference to the flowchart of FIG. 2. In FIG. 2, the boxes corresponding to optional stepsare represented in dotted lines. When appropriate, reference is made tothe diagrams of FIGS. 1A-1H.

In a first step 21, a dielectric layer 12 is deposited over the uppersurface of a substrate 11, e.g. a semiconductor substrate at the uppersurface of which at least one component has previously been designed.Such components may comprise MOS, CMOS and/or bipolar transistors,diodes, and the like. The dielectric material is selected from a groupcomprising silicon oxide (SiX) such as silicon dioxide (SiO2), fluorinedoped silicon dioxide also known as fluorine doped silicon glass (FSG),and carbon incorporated silicon oxide (SiOC).

In an optional planarization step 22, the dielectric layer 12 issmoothed, e.g. by a chemical-mechanical polishing (CMP) process.

In step 23, an insulating etch stop layer 13 is deposited above thedielectric layer 12. In a preferred embodiment, this etch stop layer ismade of SiC. The stop layer material exhibits a lower etch rate comparedto the dielectric layer. This insulating material can present a low-kcharacteristic (lower k-value than silicon oxide or silicon nitride),hence reducing the capacitive coupling between interconnect lines.Finally, it does not comprise any oxygen. The layer 13 is deposited overthe oxide layer 12, e.g. using chemical vapor deposition (CVD) withappropriate recipe, giving the structure in FIG. 1A. As will beemphasized later, SiC layer 13 is used as a buried stop layer for latermetal 15 etching.

Advantageously, the scratches induced by the dielectric layer CMP (step22) are filled with SiC, instead of the conductive glue and/or barrierlayer as by known methods. Hence, the risk of metal short is greatlyreduced.

When necessary, steps 21-23 are followed by steps of forming verticalinterconnects (i.e., contacts or vias) within the dielectric layer 12,to connect respective areas of the underlying layer (here the substrate11, or alternatively an underlying metal layer corresponding to a lowermetallization level).

Contact and via forming processes first comprise conventional steps ofdepositing and of patterning 24 a resist layer 14 for contact or vialithography, giving the structure of FIG. 1B. The resist layer ispatterned according to the desired contact or via pattern.

In step 25, a SiC specific etching process is carried out through theopenings in patterned resist layer 14, to remove the exposed portion ofthe SiC layer 13. Suitable methods for etching SiC are, in particular,dry etching methods, such as reactive ion etching (RIB), ion beametching (IBE), or etching methods in the gas phase. The desired contactor via pattern is positively transferred in the SiC layer, giving thestructure of FIG. 1C.

In step 26, exposed portions of the dielectric layer 12 are etchedthrough the openings in the resist mask 14 to form contact or via holes.This etching process is performed according to a common dielectricremoving process. The resulting structure is shown in FIG. 1D. Theremaining resist layer 14 is then removed. Alternatively, contact or viaetching may advantageously be carried out after removing the remainingresist layer, by using the patterned SiC stop layer 13 as a hard mask.

To finish the contact or via forming according to a firstimplementation, a conductive material, i.e. a metal such as AL W, Cu,Ti, TiN, Ta, TaN or combinations thereof, is then deposited to fill thecontact or via holes (step 27) to form the contacts or vias 15.Typically, contacts and vias material comprises W. Then, in step 28,etch back or chemical-mechanical polishing is used to planarize thecontacts or vias 15, while advantageously stopping on the SiC layer 13used as a stop layer for this etch or CMP process. This provision allowsto limit the erosion of the dielectric layer during the etch or CMPprocess. The structure thus obtained is depicted in FIG. 1E.

Typically, contacts or vias material comprise W. As is common practise,a thin Ti layer and further a thin TiN layer are deposited into thecontact or via holes before tungsten deposition, to help adhesion ofmetal to the underlying material.

The method is then continued in step 29 by depositing a conductivematerial, i.e. a metal such as Al, W, Cu, Ti, TiN, Ta, TaN orcombination thereof, thereby forming a metal layer 15′ for horizontalinterconnects (i.e., wires). In one embodiment, the metal layer 15′ isapplied by evaporation or sputtering. The structure thus obtained isdepicted in FIG. 1F. Typically, wires material comprises Al. As is wellknown, a thin Ti layer and possibly also a thin layer of TiN isdeposited before the Al layer 15′. Besides, another thin TiN layer mightbe deposited over the Al layer 15′.

The method further comprises a step of metal layer lithographypatterning. During this step, a resist layer 16 is applied above themetal layer 15′. Layer 16 is then patterned according to a conventionalphotolithography process to define openings corresponding to the patternof the desired wires. The resulting structure is shown in FIG. 1G.

The method ends with step 31 where the metal layer 15′ is etched throughthe openings in the patterned resist layer 16, while advantageouslystopping on the SiC layer 13 used as a stop layer for metal etching.Step 31 typically comprises main etch and overetch substeps. The desiredwires pattern is thus positively transferred in the metal layer 15′. Theerosion of the underlying dielectric layer 12 is limited thanks to theremaining SiC stop layer 13. The plasma etch recipe comprises a gasmixture which typically contains halogen or halogen based gases. Wherethe metal to be etched is Al, the gas mixture might be selected from thegroup containing boron trichloride (BCl3), hydrogen chloride (orhydrochloric acid, HCl), hydrogen bromide (HBr) and hydrogen iodine(HI). Where the metal to be etched is W, the gas mixture might besulfure hexafluoride (SF6) or other fluor-containing gases. The resistmask 16 is then removed by a process such as ashing or wet chemicalstripping without damaging the underlying metal layer 15′ and SiC layer13, to produce the final structure of FIG. 1H.

Additional vias and/or wirings might be fabricated in othermetallization levels by repeating the steps shown in FIGS. 1B-1H for anupper metallization level.

Steps 27 are 28 are optional. Typically, these steps are carried outunless contacts or vias are made of the same metal as wires, e.g. Al.Such being the case, the method simply jumps from step 26 to step 29.

It will be appreciated that SiC has been mentioned above only as apreferred example for the stop layer material. Other materials might beconsidered as possible candidates, depending on the nature of the gasmixture used for plasma etching. In particular, the stop layer materialmight be selected in a group of silicon-and carbon-containing materials,e.g. the group comprising SiC, SiCN, SiBC, SiBCN, and combinationsthereof. Depending on its nature, the stop layer material might bedeposited at step 23 by a plasma deposition method, a sputter depositionmethod (e.g. for SiCN), a spin-on method, or a CVD method (e.g. forSiC).

1. Subtractive method of manufacturing a metal interconnects structureon a substrate, comprising the steps of: depositing a dielectric layerabove the substrate; depositing a stop layer above the dielectric layer,which exhibits a lower etch rate compared to the dielectric layer;depositing a metal layer above the stop layer; depositing a first resistlayer above the metal layer; patterning the first resist layer accordingto a first desired pattern; and, etching the metal layer through thepatterned first resist layer, while stopping on the stop layer.
 2. Themethod of claim 1, further comprising, before metal deposition, thesteps of: depositing a second resist layer above the stop layer;patterning the resist layer according to a second desired pattern;etching the stop layer through the patterned second resist layer; and,etching the dielectric layer for forming contact or via holes.
 3. Themethod of claim 2, wherein etching of the dielectric layer is performedthrough the patterned second resist layer and the patterned stop layer.4. The method of claim 2, wherein etching of the dielectric layer isperformed, after removal of the remaining second resist layer, by usingthe patterned stop layer as a hard mask.
 5. The method of claim 2,further comprising, still before metal deposition, the steps of: fillingthe contacts holes with metal for forming contacts; and, planarizing thecontacts by etch back or chemical-mechanical polishing and using thepatterned stop layer as a stop layer.
 6. The method of claim 1, whereinthe stop layer material is selected from the group comprising SiC, SiCN,SiBC, SiBCN, and combinations thereof.
 7. Metal interconnect structurecomprising: a substrate; a dielectric layer lying above the substrate; astop layer for metal etching, lying above the dielectric layer whichexhibits a lower etch rate compared to the dielectric layer; a metallayer lying above the stop layer, said metal layer being patternedaccording to a first desired pattern.
 8. The metal interconnectstructure of claim 7, wherein said dielectric layer and said stop layerare both patterned according to a second desired pattern.
 9. A metalinterconnect structure comprising: a substrate; a dielectric layer lyingabove the substrate; a stop layer for metal etching, lying above thedielectric layer which exhibits a lower etch rate compared to thedielectric layer: a metal layer lying above the stop layer, said metallayer being patterned according to a first desired pattern wherein themetal interconnect structure is obtained by a method comprising,depositing a dielectric layer above the substrate; depositing a stoplayer above the dielectric layer, which exhibits a lower etch ratecompared to the dielectric layer; depositing a metal layer above thestop layer; patterning the first resist layer according to a firstdesired pattern; and, etching the metal layer through the patternedfirst resist layer, while stopping on the stop layer.
 10. The metalinterconnect structure of claim 7, wherein the metal layer material isat least one metal selected from the group comprising Al, W, Cu, Ti,TiN, Ta, TaN and combinations thereof.
 11. The metal interconnectstructure of claim 8, wherein the patterned dielectric layer and thepatterned stop layer define contacts holes filled with metal.
 12. Themetal interconnect structure of claim 11, wherein the metal filling thecontacts holes is at least one metal selected from the group comprisingAl, W, Cu, Ti, TiN, Ta, TaN and combinations thereof.
 13. The metalinterconnect structure of claim 7, wherein the stop layer material isselected from the group comprising SiC, SiCN, SiBC, SiBCN, andcombinations thereof.
 14. Semiconductor device comprising aninterconnect structure according to claim
 7. 15. Integrated circuit chipcomprising an interconnect structure according to claim
 7. 16.Electronic apparatus comprising an interconnect structure according toclaim
 7. 17. Electronic apparatus comprising a semiconductor deviceaccording to claim
 14. 18. Electronic apparatus comprising an integratedcircuit chip according to claim 15.